In various memories, such as dynamic random access memory (DRAM), data may be read from or provided to memory cells over digit lines using sense amplifiers. Typically, sense amplifiers are coupled to digit lines and are configured to sense data on the digit lines and amplify the sensed data. In between various operations in which sense amplifiers provide data to and/or receive data from respective memory cells, charge may leak from or to one or more memory cells, resulting in corruption of data.
In operation, one or more digit lines may be held at a relatively high supply voltage, such as an internal supply voltage VDD, and charge may leak into memory cells storing a logical “0” and corrupt data stored therein. The longer a digit line is held at the relatively high supply voltage, the greater the chance of data being corrupted as a result of the leakage. A measurement of memory performance may be how long a memory cell retains data under these circumstances. As memory density and complexity has increased over time, retention of memory cells under these circumstances has decreased. For example, in the industry transition to smaller memory cell configurations, data retention has decreased significantly. While in some instances, it may be possible to ensure that a digit line is not maintained at the relatively high supply voltage, this approach may not be available for all desired memory implementations.